Electronic Circuits XII: Clocks, Latches, and Timing Closure Step by Step
A lightweight execution-visualization book.
Clock Edges Are Indexed Events
Clock Period Spaces Every Edge
Selected Edge Is a Source, Not a Caption
Faster Clock Tightens the Same Kind of Ledger
Setup and Hold Are Windows
Data Arrives Before the Setup Window Closes
Zero Slack Is Still a Passing Boundary
Late Data Fails Setup Before Capture
Early Next Change Fails Hold After Capture
Delays and State Elements
Stage Delays Add Before the Next Edge
One Extra Delay Breaks the Same Path
Transparent Latch Captures Only Inside Its Window
Capture and Timing Closure Audit
Edge Capture Updates State Only After a Passing Window
Failed Window Keeps the Prior State
Timing Closure Audit Cites Every Source
Timing Relation Cross Scans
Clock Edge Time Three-Row Scan
Setup Hold Slack Three-Row Scan
Delay Budget Three-Row Scan
Latch Window Three-Row Scan
Edge Capture State Three-Row Scan
Timing Boundary Depth Scans
Setup Requirement Boundary Three-Row Scan
Hold Requirement Boundary Three-Row Scan
Delay Repartition Three-Row Scan
Latch Open Width Three-Row Scan
Capture Source Gate Three-Row Scan