Late Data Fails Setup Before Capture - Electronic Circuits XII: Clocks, Latches, and Timing Closure Step by Step

Negative setup slack rejects the capture attempt. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

Late data makes setup slack negative

Data arrives at 7 seconds, only 1 second before the selected edge.

8\ \text{s}+(-7\ \text{s})+(-2\ \text{s})=-1\ \text{s}

Later arrivals cross from boundary to setup failure

The next-change row stays safely after hold while arrival moves across the setup boundary.

\begin{array}{c|c|c}t_D&s_{\text{setup}}&\text{gate}\\6\ \text{s}&0\ \text{s}&\text{pass}\\7\ \text{s}&\mathord{-}1\ \text{s}&\text{fail}\\8\ \text{s}&\mathord{-}2\ \text{s}&\text{fail}\\\end{array}

The attempted capture is rejected before state changes

The setup slack is -1 second, so this timing check rejects the capture.

\text{accepted bit}=0