Accepted duty rows are checked against an output-voltage ceiling. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

1/3 duty row

Input stays 12 V. Accepted duty 1/3 gives output 4 V against a 6 V ceiling, so margin is 2 V.

Vo=4 V,m=2 VpassV_o=4\ \text{V},\quad m=2\ \text{V}\Rightarrow\text{pass}
Buck output-ceiling boundaryDuty is accepted only after the ramp balance check.L 3 HV 8 Vdt 1 sIi 0 AdI 8/3 AIf 8/3 AL 3 HV -4 Vdt 2 sIi 8/3 AdI -8/3 AIf 0 Asum Vdt 0 V*sgate passVin 12 VD 1/3Vout 4 V

1/2 duty row

Input stays 12 V. Accepted duty 1/2 gives output 6 V against a 6 V ceiling, so margin is 0 V.

Vo=6 V,m=0 VpassV_o=6\ \text{V},\quad m=0\ \text{V}\Rightarrow\text{pass}
Buck output-ceiling boundaryDuty is accepted only after the ramp balance check.L 3 HV 6 Vdt 1 sIi 0 AdI 2 AIf 2 AL 3 HV -6 Vdt 1 sIi 2 AdI -2 AIf 0 Asum Vdt 0 V*sgate passVin 12 VD 1/2Vout 6 V

2/3 duty row

Input stays 12 V. Accepted duty 2/3 gives output 8 V against a 6 V ceiling, so margin is negative 2 V.

Vo=8 V,m=2 VfailV_o=8\ \text{V},\quad m=-2\ \text{V}\Rightarrow\text{fail}
Buck output-ceiling boundaryDuty is accepted only after the ramp balance check.L 3 HV 4 Vdt 2 sIi 0 AdI 8/3 AIf 8/3 AL 3 HV -8 Vdt 1 sIi 8/3 AdI -8/3 AIf 0 Asum Vdt 0 V*sgate passVin 12 VD 2/3Vout 8 V