A packet-current row can be viewed as a finite resistance ledger. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.
highlighted = computed this step
Equivalent resistance reuses the packet voltage and current
The resistance row is accepted only if its voltage difference matches the cited packet row.
ΔV=4VI=4A
A faster packet clock lowers the equivalent resistance
Each row keeps the same packet swing and recomputes current and resistance.
f41Hz21Hz1HzIavg2A4A8AReq2ohm1ohm21ohm
The packet row gives an equivalent resistance
The resistance uses the same voltage difference as the cited packet row.