faster-clock-doubles-average-current - Electronic Circuits XVI: Switched-Capacitor Charge and Conversion Step by Step

Changing clock frequency changes average packet current. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

Frequency counts identical packets per second

The packet size is fixed before the clock row changes the average current.

\Delta Q=6\ \text{C}\quad f=4\ \text{Hz}

Current scales directly with clock frequency

The capacitance and voltage swing stay fixed; each row changes only f.

\begin{array}{c|c|c}f&\Delta Q&I_{\text{avg}}\\1\ \text{Hz}&6\ \text{C}&6\ \text{A}\\2\ \text{Hz}&6\ \text{C}&12\ \text{A}\\4\ \text{Hz}&6\ \text{C}&24\ \text{A}\\\end{array}

A faster clock sends more packets per second

The capacitance and voltage swing stay fixed; only the clock row changes.

6\ \text{C}\cdot4\ \text{Hz}=24\ \text{A}