A stacked output is a sum of source voltage and flying-capacitor voltage. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

Stacked output has a source part and a flying-capacitor part

A one-factor scan can hide the topology; this cross scan keeps both addends visible.

Vout=Vs+VflyV_{\text{out}}=V_s+V_{\text{fly}}
Stacked phase outputThe phase row binds source, flying capacitor, and output.Vs 6 VVfly 4 VVout 10 V

Either addend moves the stacked output

The first three rows change the source rail; the next three rows change the flying-capacitor voltage.

scanVsVflyVoutVs changes4 V4 V8 VVs changes6 V4 V10 VVs changes8 V4 V12 VVfly changes6 V2 V8 VVfly changes6 V4 V10 VVfly changes6 V6 V12 V\begin{array}{c|c|c|c}\text{scan}&V_s&V_{\text{fly}}&V_{\text{out}}\\V_s\ \text{changes}&4\ \text{V}&4\ \text{V}&8\ \text{V}\\V_s\ \text{changes}&6\ \text{V}&4\ \text{V}&10\ \text{V}\\V_s\ \text{changes}&8\ \text{V}&4\ \text{V}&12\ \text{V}\\V_{\text{fly}}\ \text{changes}&6\ \text{V}&2\ \text{V}&8\ \text{V}\\V_{\text{fly}}\ \text{changes}&6\ \text{V}&4\ \text{V}&10\ \text{V}\\V_{\text{fly}}\ \text{changes}&6\ \text{V}&6\ \text{V}&12\ \text{V}\\\end{array}

The final stacked row adds two cited voltages

The output label is accepted only from the declared stack topology.

6 V+4 V=10 V6\ \text{V}+4\ \text{V}=10\ \text{V}
Stacked phase outputThe phase row binds source, flying capacitor, and output.Vs 6 VVfly 4 VVout 10 V