A switched-capacitor-has-equivalent-resistance scan reuses the packet voltage difference and average packet current, checking that the equivalent resistance R_eq = delta-V / I_avg closes the same current ledger row by row. The arithmetic is exact only for the stated voltage differences, packet charges, clock rates, currents, equivalent resistances, and rows in the ideal capacitor, ideal switch, nonoverlap-clock model. Real switched-capacitor converters add switch resistance, ESR, parasitic capacitance, charge injection, clock jitter, load current, probe/calibration limits, finite precision, and measurement uncertainty.

A packet-current row can be viewed as a finite resistance ledger. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

Equivalent resistance reuses the packet voltage and current

The resistance row is accepted only if its voltage difference matches the cited packet row.

ΔV=4 VI=4 A\Delta V=4\ \text{V}\quad I=4\ \text{A}
Switched-capacitor resistanceThe resistance row cites the packet row.C 2 FdV 4 Vfsw 1/2 HzQpacket 8 CIavg 4 AdV 4 VReq 1 ohm

A faster packet clock lowers the equivalent resistance

Each row keeps the same packet swing and recomputes current and resistance.

fIavgReq14 Hz2 A2 ohm12 Hz4 A1 ohm1 Hz8 A12 ohm\begin{array}{c|c|c}f&I_{\text{avg}}&R_{\text{eq}}\\\tfrac{1}{4}\ \text{Hz}&2\ \text{A}&2\ \text{ohm}\\\tfrac{1}{2}\ \text{Hz}&4\ \text{A}&1\ \text{ohm}\\1\ \text{Hz}&8\ \text{A}&\tfrac{1}{2}\ \text{ohm}\\\end{array}

The packet row gives an equivalent resistance

The resistance uses the same voltage difference as the cited packet row.

4 V/4 A=1 ohm4\ \text{V}/4\ \text{A}=1\ \text{ohm}
Switched-capacitor resistanceThe resistance row cites the packet row.C 2 FdV 4 Vfsw 1/2 HzQpacket 8 CIavg 4 AdV 4 VReq 1 ohm