A faster-clock-doubles-average-current scan holds the charge packet fixed and raises the switching frequency across rows, checking that I_avg = delta-Q * f rises in direct proportion to clock rate. The arithmetic is exact only for the stated packet charges, clock rates, currents, and rows in the ideal capacitor, ideal switch, nonoverlap-clock model. Real switched-capacitor converters add switch resistance, ESR, parasitic capacitance, charge injection, clock jitter, load current, probe/calibration limits, finite precision, and measurement uncertainty.
Changing clock frequency changes average packet current. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.
highlighted = computed this step
Frequency counts identical packets per second
The packet size is fixed before the clock row changes the average current.
ΔQ=6Cf=4Hz
Current scales directly with clock frequency
The capacitance and voltage swing stay fixed; each row changes only f.
f1Hz2Hz4HzΔQ6C6C6CIavg6A12A24A
A faster clock sends more packets per second
The capacitance and voltage swing stay fixed; only the clock row changes.