A stacked switched-capacitor phase adds the source voltage and flying-capacitor voltage, so the flying voltage controls whether the output hits a ceiling. The flying-capacitor rows 2, 4, and 6 V produce 8, 10, and 12 V against a 10 V limit exactly for the ideal stacking model; real converters add switch drops, charge injection, parasitic capacitance, leakage, ESR, clock timing error, load variation, ripple, and voltage measurement uncertainty.

A stacked phase output is checked against a voltage ceiling. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

The stacked phase is checked against an output ceiling

The source stays fixed while the flying-capacitor voltage changes.

Vout=Vs+VflyVmax⁡=10 VV_{\text{out}}=V_s+V_{\text{fly}}\quad V_{\max}=10\ \text{V}
Stacked output ceilingThe phase topology computes the output voltage.Vs 6 VVfly 4 VVout 10 Vmargin 0 Vpass

Three flying-capacitor voltages cross the output ceiling

The topology is the same in all rows; only the flying-capacitor voltage changes.

VflyVoutm2 V8 V2 V4 V10 V0 V6 V12 V−2 V\begin{array}{c|c|c}V_{\text{fly}}&V_{\text{out}}&m\\2\ \text{V}&8\ \text{V}&2\ \text{V}\\4\ \text{V}&10\ \text{V}&0\ \text{V}\\6\ \text{V}&12\ \text{V}&\mathord{-}2\ \text{V}\\\end{array}
Stacked output ceilingThe phase topology computes the output voltage.Vs 6 VVfly 4 VVout 10 Vmargin 0 Vpass

The final stacked output is above the ceiling

The last row computes a voltage above the ceiling, leaving a negative margin.

m=−2 Vfailm=\mathord{-}2\ \text{V}\quad \text{fail}
Stacked output ceilingThe phase topology computes the output voltage.Vs 6 VVfly 6 VVout 12 Vmargin -2 Vfail