A packet-current budget treats each switched-capacitor cycle as a fixed charge packet, then checks how clock frequency turns that packet into average current. The rows are exact only for the declared capacitance, voltage swing, frequency, ideal switches and capacitors, and lossless charge transfer; real converters add switch resistance, charge injection, clock feedthrough, leakage, capacitor tolerance, ESR, parasitics, finite settling, thermal drift, and voltage/current/time measurement uncertainty.
A packet-current budget is checked by changing only clock frequency. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.
highlighted = computed this step
The current budget starts from a fixed packet size
Capacitance and swing are fixed, so the packet size is fixed before the clock changes.
Iavg=ΔQfImax=6A
Three clock rates show the current boundary
The half-hertz row is below the budget, the one-hertz row is exact, and the fast row fails.
f21Hz1Hz23HzΔQ6C6C6CIavg3A6A9Am3A0A−3A
The fast clock fails because average current is above budget
The final clock gives too much average current, so the current margin is negative.