A secondary reset-voltage limit scan first accepts the primary reset balance, then checks whether the secondary pulse stays under its ceiling. The margins are exact only for the declared turns ratio, primary voltage, reset interval, ideal coupling, and lossless transformer assumptions; real designs include leakage inductance, winding resistance, diode or switch drops, magnetizing current, core saturation, parasitics, heating, and voltage/time measurement uncertainty.
Balanced primary reset rows can still exceed a secondary pulse ceiling. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.
highlighted = computed this step
Reset row 1
Primary reset is balanced first. Secondary turns 1 give secondary on-pulse 3 V against a 6 V ceiling, so margin is 3 V.
m=3Vpass
Reset row 2
Primary reset is balanced first. Secondary turns 2 give secondary on-pulse 6 V against a 6 V ceiling, so margin is 0 V.
m=0Vpass
Reset row 3
Primary reset is balanced first. Secondary turns 3 give secondary on-pulse 9 V against a 6 V ceiling, so margin is negative 3 V.