reset-interval-balances-core-volt-seconds - Electronic Circuits XV & XVI: Transformers and Switched-Capacitor Conversion Step by Step

A reset-interval-balances-core-volt-seconds scan checks that primary and secondary volt-second ledgers both close over the switching cycle. The 12 V on interval and -6 V reset interval balance to 0 V*s only for the stated ideal coupled-reset rows. Real transformers add magnetizing-current limits, leakage inductance, core loss, saturation margin, winding resistance, timing error, finite precision, and measurement uncertainty.

Repeatable switching needs a source-bound reset balance. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

A reset pair must first balance primary volt-seconds

The coupled reset check is downstream of an accepted primary balance and the same transformer voltage row.

\sum V_p\Delta t=0\ \text{V}\cdot\text{s}\quad\Rightarrow\quad \sum V_s\Delta t=0\ \text{V}\cdot\text{s}

Balanced primary rows give balanced secondary rows

Each scan row uses one accepted primary on/off pair and one matching transformer voltage.

\begin{array}{c|c|c|c|c}V_{p,\text{on}}&V_{p,\text{off}}&\sum V_p\Delta t&\sum V_s\Delta t&\text{gate}\\6\ \text{V}&-3\ \text{V}&0\ \text{V}\cdot\text{s}&0\ \text{V}\cdot\text{s}&\text{pass}\\8\ \text{V}&-4\ \text{V}&0\ \text{V}\cdot\text{s}&0\ \text{V}\cdot\text{s}&\text{pass}\\12\ \text{V}&-6\ \text{V}&0\ \text{V}\cdot\text{s}&0\ \text{V}\cdot\text{s}&\text{pass}\\\end{array}

Coupled reset derives secondary volt-seconds from the same primary rows

The accepted reset row must cite the same transformer primary voltage and the same interval ids.

12\ \text{V}\cdot1\ \text{s}+(-6\ \text{V})\cdot2\ \text{s}=0\ \text{V}\cdot\text{s}\quad V_{s,\text{total}}=0\ \text{V}\cdot\text{s}