An equal-series-caps-split-rail scan requires two equal capacitances and varies the source rail across three rows, checking that the midpoint V_mid = V_s / 2 splits the rail only when C_a = C_b row by row. The arithmetic is exact only for the stated source voltages, midpoint voltages, capacitances, and rows in the ideal capacitor, switch, and phase-topology model. Real switched-capacitor converters add switch resistance, ESR, parasitic capacitance, charge injection, timing skew, load current, probe/calibration limits, finite precision, and measurement uncertainty.
A symmetric split is accepted only from equal capacitor sources. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.
highlighted = computed this step
A split row first proves the two capacitances match
The midpoint is accepted only from two equal-capacitance sources across the same rail.
Ca=Cb=2FVs=8V
Equal split keeps the midpoint at one half of the rail
Each row rebuilds the split from two equal capacitors and a different source rail.
Vs8V10V12VVmid4V5V6Vsourcesequalequalequal
Equal source capacitors split the rail
The split row cites two equal capacitance sources before accepting the midpoint.