A steady inductor switching ledger needs balanced volt-seconds. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

The accepted pair has one up-ramp and one down-ramp

Both rows must use the same inductance. The signed volt-seconds decide whether the ripple returns to its start.

VLΔt=0ΔI=0 A\sum V_L\Delta t=0\quad\Leftrightarrow\quad \sum\Delta I=0\ \text{A}
Volt-second balance setupThe accepted pair returns the inductor current to its start.L 3 HV 9 Vdt 1 sIi 0 AdI 3 AIf 3 AL 3 HV -3 Vdt 3 sIi 3 AdI -3 AIf 0 Asum Vdt 0 V*sgate pass

The gate rejects nonzero volt-seconds

The first two rows balance exactly. The shorter off interval leaves a positive volt-second total and fails.

VonΔtonVoffΔtoffVΔtgate9 Vs9 Vs0 Vspass6 Vs6 Vs0 Vspass9 Vs6 Vs3 Vsfail\begin{array}{c|c|c|c}V_{\text{on}}\Delta t_{\text{on}}&V_{\text{off}}\Delta t_{\text{off}}&\sum V\Delta t&\text{gate}\\9\ \text{V}\cdot\text{s}&-9\ \text{V}\cdot\text{s}&0\ \text{V}\cdot\text{s}&\text{pass}\\6\ \text{V}\cdot\text{s}&-6\ \text{V}\cdot\text{s}&0\ \text{V}\cdot\text{s}&\text{pass}\\9\ \text{V}\cdot\text{s}&-6\ \text{V}\cdot\text{s}&3\ \text{V}\cdot\text{s}&\text{fail}\\\end{array}

Steady switching requires zero volt-seconds and zero net current change

The accepted pair uses one common inductor. A shorter off interval leaves positive volt-seconds and is rejected.

9 V1 s+(3 V)3 s=0 Vs;3 Vs is rejected9\ \text{V}\cdot1\ \text{s}+\left(-3\ \text{V}\right)\cdot3\ \text{s}=0\ \text{V}\cdot\text{s}\quad;\quad3\ \text{V}\cdot\text{s}\ \text{is rejected}
Volt-second acceptance gateOnly the balanced on/off pair is accepted.L 3 HV 9 Vdt 1 sIi 0 AdI 3 AIf 3 AL 3 HV -3 Vdt 3 sIi 3 AdI -3 AIf 0 Asum Vdt 0 V*sgate passL 3 HV -3 Vdt 2 sIi 3 AdI -2 AIf 1 Asum Vdt 3 V*sgate fail