Topology Row Audit - Electronic Circuits IV: Digital Logic Signals and Switch Networks Step by Step

Series and parallel switch networks produce different accepted tables from the same input rows. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

A series pull-down needs every switch closed

The rendered NAND row has one open series switch, so the output stays HIGH. The next table recomputes every input pair from that series topology.

\text{series path open}\Rightarrow Y=1

The NAND table is regenerated from the series path

Each compact cell is a helper output. The table is not a copied label; it is the four-row audit of the series switch network.

\begin{array}{ccc} A&B&Y\\0&0&1\\0&1&1\\1&0&1\\1&1&0\end{array}

A parallel pull-down needs any closed branch

The same LOW,HIGH input row has a different result in the NOR network because the high input closes one parallel branch.

\text{parallel branch closed}\Rightarrow Y=0

The NOR table is regenerated from the parallel graph

Every NOR row is recomputed from branch reachability. The all-low row remains HIGH because neither branch reaches ground.

\begin{array}{ccc} A&B&Y\\0&0&1\\0&1&0\\1&0&0\\1&1&0\end{array}

One input row proves labels are not the source

For the shared LOW,HIGH row, NAND yields HIGH while NOR yields LOW. The difference comes from series versus parallel wiring.

\text{LOW,HIGH row}:\quad Y_{\text{NAND}}=1,\quad Y_{\text{NOR}}=0