Logic Threshold Boundary Scan - Electronic Circuits IV: Digital Logic Signals and Switch Networks Step by Step

A static logic input is trusted only after below, boundary, middle, and above-threshold rows are shown. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

The scan states the accepted voltage bands first

The same low and high thresholds are reused for every row. Values at or below the low threshold are LOW; values at or above the high threshold are HIGH.

V_{\text{in}}\le 1\ \text{V}\Rightarrow\text{LOW},\quad V_{\text{in}}\ge 4\ \text{V}\Rightarrow\text{HIGH}

Five voltage rows expose both boundaries

The table includes below, equality, middle, equality, and above cases. That makes the invalid band a checked row instead of a caption.

\begin{array}{c|c|c|c}V_{\text{in}}&V_{\text{LOW}}&V_{\text{HIGH}}&\text{state}\\0\ \text{V}&1\ \text{V}&4\ \text{V}&\text{LOW}\\1\ \text{V}&1\ \text{V}&4\ \text{V}&\text{LOW}\\2\ \text{V}&1\ \text{V}&4\ \text{V}&\text{INVALID}\\4\ \text{V}&1\ \text{V}&4\ \text{V}&\text{HIGH}\\5\ \text{V}&1\ \text{V}&4\ \text{V}&\text{HIGH}\\\end{array}

Both equality rows are explicit

The low-edge row is 1 volt and the high-edge row is 4 volts. The accepted states come from the same classifier.

1\ \text{V}\Rightarrow\text{LOW},\quad 4\ \text{V}\Rightarrow\text{HIGH}

The middle row still stops the logic chain

The middle input is 2 volts, so this static logic model marks it INVALID before a switch network may consume it.

1\ \text{V}<2\ \text{V}<4\ \text{V}\Rightarrow\text{INVALID}