Level Margin Band Scan - Electronic Circuits IV & XII: Digital Logic and Timing Closure Step by Step

A logic input is classified by fixed low and high voltage thresholds, so the boundary rule shows up as scan rows instead of prose. With a 1 V low threshold and 4 V high threshold the 0, 1, 2, 4, and 5 V inputs sort into LOW, LOW, INVALID, HIGH, and HIGH exactly for the ideal threshold model; real logic adds threshold spread, fanout loading, leakage, propagation delay, supply variation, contact resistance, noise, temperature drift, and voltage measurement uncertainty.

A logic input is accepted only after low, middle, and high voltage cases are checked against the same thresholds. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

A logic input is a banded voltage measurement

The scan fixes the low and high thresholds, then varies only the input voltage. That makes the boundary rule visible as rows, not as prose.

V_{\text{in}}\le 1\ \text{V}\Rightarrow\text{LOW},\quad V_{\text{in}}\ge 4\ \text{V}\Rightarrow\text{HIGH}

Five rows show below, edge, middle, edge, and above

The reader can scan the input column downward and see exactly where the accepted LOW band ends and the accepted HIGH band begins.

\begin{array}{c|c|c|c}V_{\text{in}}&V_{\text{LOW}}&V_{\text{HIGH}}&\text{state}\\0\ \text{V}&1\ \text{V}&4\ \text{V}&\text{LOW}\\1\ \text{V}&1\ \text{V}&4\ \text{V}&\text{LOW}\\2\ \text{V}&1\ \text{V}&4\ \text{V}&\text{INVALID}\\4\ \text{V}&1\ \text{V}&4\ \text{V}&\text{HIGH}\\5\ \text{V}&1\ \text{V}&4\ \text{V}&\text{HIGH}\\\end{array}

The middle row is a rejected measurement

The middle row is not rounded to a bit. It blocks the ideal logic chain because it is greater than the low threshold and less than the high threshold.

1\ \text{V}<2\ \text{V}<4\ \text{V}\Rightarrow\text{INVALID}