A late-data-fails-setup-before-capture ledger shows the setup gate rejecting a capture when data reaches the latch too close to the clock edge. The 7 s data arrival against an 8 s edge and 2 s setup window gives -1 s slack only inside the stated ideal timing-row model. Real circuits add skew, jitter, PVT variation, metastability probability, path-delay distributions, instrument calibration limits, finite precision, and measurement uncertainty.
Negative setup slack rejects the capture attempt. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.
highlighted = computed this step
Late data makes setup slack negative
Data arrives at 7 seconds, only 1 second before the selected edge.
8s+(−7s)+(−2s)=−1s
Later arrivals cross from boundary to setup failure
The next-change row stays safely after hold while arrival moves across the setup boundary.
tD6s7s8sssetup0s−1s−2sgatepassfailfail
The attempted capture is rejected before state changes
The setup slack is -1 second, so this timing check rejects the capture.