Early Next Change Fails Hold After Capture - Electronic Circuits IV & XII: Digital Logic and Timing Closure Step by Step

Hold time protects the captured value after the clock edge, so a next data change that arrives too early can invalidate an otherwise planned capture. The seconds in this ledger are exact training times for the setup/hold inequality; real timing closure uses characterized device delays, clock uncertainty, metastability risk, and measurement margins.

Negative hold slack rejects the capture attempt. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

An early next change makes hold slack negative

The next data change is at 17/2 seconds, which is too soon after the edge.

{17\over 2}\ \text{s}+(-8\ \text{s})+(-1\ \text{s})={-1\over 2}\ \text{s}

Earlier next-change rows cross the hold boundary

The data-arrival row stays safely before setup while the next change moves toward the edge.

\begin{array}{c|c|c}t_{\text{next}}&s_{\text{hold}}&\text{gate}\\9\ \text{s}&0\ \text{s}&\text{pass}\\\tfrac{17}{2}\ \text{s}&\mathord{-}\tfrac{1}{2}\ \text{s}&\text{fail}\\\tfrac{33}{4}\ \text{s}&\mathord{-}\tfrac{3}{4}\ \text{s}&\text{fail}\\\end{array}

The hold failure rejects the same capture attempt

The hold slack is -1/2 seconds, so the status is rejected.

\text{accepted bit}=0