This labels-cannot-override-wires lesson checks that the accepted NAND or NOR table comes from the actual series or parallel pull-down topology, not from a handwritten label. Different wire graphs produce different LOW rows, so the logic name is only trusted after the topology audit closes. Real gates still have threshold windows, finite drive, leakage, delay, fanout limits, noise margins, tolerances, and measurement uncertainty.
A compact table is useful only because its cells are regenerated from the switch topology. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.
highlighted = computed this step
A wrong NAND label cannot override wires
The NAND table is generated from the same series pull-down topology used in the diagram.
A0011B0101Y1110
A NOR table is a different topology audit
The NOR table is generated from parallel pull-down branches. The lesson never copies NAND cells into NOR by hand.
A0011B0101Y1000
Different wires give different accepted tables
The compact tables are accepted because each output cell is recomputed from the corresponding topology. The names NAND and NOR are not enough; the wire graph decides which rows are LOW.