Invalid Band Is Not a State - Electronic Circuits IV & XII: Digital Logic and Timing Closure Step by Step

An invalid-band-is-not-a-state scan checks middle voltages that fall between the low and high thresholds and rejects them as INVALID rather than coercing them into LOW or HIGH row by row. The arithmetic is exact only for the stated input voltages, thresholds, rejected states, and rows in the ideal threshold-logic model. Real gates add noise-margin limits, supply tolerance, input leakage, finite rise time, loading, probe/calibration limits, finite precision, and measurement uncertainty.

A middle voltage is rejected in this ideal logic model instead of being guessed into LOW or HIGH. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

A middle voltage is rejected

An input of 2 volts is above the low threshold and below the high threshold.

1\ \text{V} < 2\ \text{V} < 4\ \text{V}

INVALID is not a third logic state

The model rejects this input before it can drive a gate. That keeps later truth tables from silently coercing the value.

\text{INVALID input} \Rightarrow \text{no gate row}