The capstone accepts one coherent transformer-coupling ledger. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

The audit accepts only a coherent transformer source chain

Transformer power, flux voltage, reflected load, and reset balance must agree before the final accepted bit is displayed.

audit=transformer+flux+load+reset\text{audit}=\text{transformer}+\text{flux}+\text{load}+\text{reset}
Transformer audit setupThe final accepted bit cites every upstream source.Np 4Ns 2Vp 12 VVs 6 VIp 1 AIs 2 APp 12 WPs 12 WNp 4Ns 2dPhi 3 Wbdt 1 sVp 12 VVs 6 Vmode aidingRload 3 ohmRref 12 ohmVp 12 VVs 6 VIp(load) 1 AIs 2 APp 12 WPs 12 Wclaim loaded reflected currentsum Vdt 0 V*sgate passsum NsVdt 0 V*sgate passL 4 HV 12 Vdt 1 sIi 0 AdI 3 AIf 3 AL 4 HV -6 Vdt 2 sIi 3 AdI -3 AIf 0 Atransformer sourceflux sourcereflected load sourcereset sourceaccepted

Load changes preserve the audit only when every cited source agrees

Each row rebuilds the full chain with a different secondary load.

RsRpPpgate6 ohm24 ohm6 Wpass3 ohm12 ohm12 Wpass2 ohm8 ohm18 Wpass\begin{array}{c|c|c|c}R_s&R_p&P_p&\text{gate}\\6\ \text{ohm}&24\ \text{ohm}&6\ \text{W}&\text{pass}\\3\ \text{ohm}&12\ \text{ohm}&12\ \text{W}&\text{pass}\\2\ \text{ohm}&8\ \text{ohm}&18\ \text{W}&\text{pass}\\\end{array}

The transformer audit cites every accepted source

The final accepted bit requires transformer power, flux voltage, reflected load, and reset balance to be one coherent source chain.

Rp=12 ohmPp=Ps=12 Waudit=acceptedR_p=12\ \text{ohm}\quad P_p=P_s=12\ \text{W}\quad \text{audit}=\text{accepted}
Transformer coupling auditEvery displayed final value cites its checked source.Np 4Ns 2Vp 12 VVs 6 VIp 1 AIs 2 APp 12 WPs 12 WNp 4Ns 2dPhi 3 Wbdt 1 sVp 12 VVs 6 Vmode aidingRload 3 ohmRref 12 ohmVp 12 VVs 6 VIp(load) 1 AIs 2 APp 12 WPs 12 Wclaim loaded reflected currentsum Vdt 0 V*sgate passsum NsVdt 0 V*sgate passL 4 HV 12 Vdt 1 sIi 0 AdI 3 AIf 3 AL 4 HV -6 Vdt 2 sIi 3 AdI -3 AIf 0 Atransformer sourceflux sourcereflected load sourcereset sourceaccepted