volt-seconds-must-balance - Electronic Circuits XIII & XIV: Power Supplies and Switching Energy Step by Step

A volt-seconds-must-balance scan checks each on/off interval pair so the signed volt-seconds sum to zero, sum V * delta-t = 0, equivalent to zero net current change row by row. The arithmetic is exact only for the stated on-voltages, off-voltages, intervals, volt-second sums, gate states, and rows in the ideal inductor and ideal switching model. Real converters add winding resistance, switch loss, diode drop, core saturation, ripple approximation, current-sense/probe calibration limits, finite precision, and measurement uncertainty.

A steady inductor switching ledger needs balanced volt-seconds. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

The accepted pair has one up-ramp and one down-ramp

Both rows must use the same inductance. The signed volt-seconds decide whether the ripple returns to its start.

\sum V_L\Delta t=0\quad\Leftrightarrow\quad \sum\Delta I=0\ \text{A}

The gate rejects nonzero volt-seconds

The first two rows balance exactly. The shorter off interval leaves a positive volt-second total and fails.

\begin{array}{c|c|c|c}V_{\text{on}}\Delta t_{\text{on}}&V_{\text{off}}\Delta t_{\text{off}}&\sum V\Delta t&\text{gate}\\9\ \text{V}\cdot\text{s}&-9\ \text{V}\cdot\text{s}&0\ \text{V}\cdot\text{s}&\text{pass}\\6\ \text{V}\cdot\text{s}&-6\ \text{V}\cdot\text{s}&0\ \text{V}\cdot\text{s}&\text{pass}\\9\ \text{V}\cdot\text{s}&-6\ \text{V}\cdot\text{s}&3\ \text{V}\cdot\text{s}&\text{fail}\\\end{array}

Steady switching requires zero volt-seconds and zero net current change

The accepted pair uses one common inductor. A shorter off interval leaves positive volt-seconds and is rejected.

9\ \text{V}\cdot1\ \text{s}+\left(-3\ \text{V}\right)\cdot3\ \text{s}=0\ \text{V}\cdot\text{s}\quad;\quad3\ \text{V}\cdot\text{s}\ \text{is rejected}