A minimum-valley-must-feed-regulator scan holds the peak and ripple fixed so the valley V_valley = V_peak - delta-V is fixed, then varies the regulator minimum across three rows, checking the gate V_valley >= V_min row by row. The arithmetic is exact only for the stated peak voltages, ripple voltages, valley voltages, minimum voltages, gate states, and rows in the ideal capacitor and ideal regulator model. Real reservoirs add ESR, capacitance tolerance, diode drops, load transients, ripple waveform shape, meter/probe calibration limits, finite precision, and measurement uncertainty.

A regulator claim needs the reservoir valley to clear the required input. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

The valley is peak minus ripple

The checked peak is 10 V and the checked ripple is 3 V, so the valley is fixed before any minimum is tested.

Vvalley=Vpeak−ΔVV_{\text{valley}}=V_{\text{peak}}-\Delta V
Reservoir valley setupThe voltage valley is computed before the pass gate.Iload 2 Adt 3 sC 2 FdV 3 VVmin 6 Vgate pass

The same valley can pass or fail different minimums

The inclusive boundary row passes exactly at the valley; a higher required minimum fails.

VpeakΔVVvalleyVmin⁡gate10 V3 V7 V6 Vpass10 V3 V7 V7 Vpass10 V3 V7 V8 Vfail\begin{array}{c|c|c|c|c}V_{\text{peak}}&\Delta V&V_{\text{valley}}&V_{\min}&\text{gate}\\10\ \text{V}&3\ \text{V}&7\ \text{V}&6\ \text{V}&\text{pass}\\10\ \text{V}&3\ \text{V}&7\ \text{V}&7\ \text{V}&\text{pass}\\10\ \text{V}&3\ \text{V}&7\ \text{V}&8\ \text{V}&\text{fail}\\\end{array}

The valley must stay above the regulator minimum

The same valley can pass one declared minimum and fail a higher one. The gate is inclusive and exact.

10 V−3 V=7 V≥6 Vbut7 V<8 V10\ \text{V}\mathbin{-}3\ \text{V}=7\ \text{V}\ge6\ \text{V}\quad\text{but}\quad7\ \text{V}<8\ \text{V}
Reservoir valley gateThe required minimum decides whether the supply can proceed.Iload 2 Adt 3 sC 2 FdV 3 VVmin 6 Vgate passIload 2 Adt 3 sC 2 FdV 3 VVmin 8 Vgate fail