NAND Requires Both Closed - Electronic Circuits IV: Digital Logic Signals and Switch Networks Step by Step

A NAND gate is modeled as a pull-up with two series pull-down switches. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

One open series switch blocks the low path

One input is HIGH and one is LOW, so one series pull-down switch is still open. The output remains 5 volts.

\text{HIGH, LOW} \Rightarrow V_{\text{out}} = 5\ \text{V}

Both closed switches pull down

When both inputs are HIGH, both series switches close. The output is 0 volts and the pull-up current is 1 ampere.

\text{HIGH, HIGH} \Rightarrow V_{\text{out}} = 0\ \text{V},\quad I = 1\ \text{A}