Invalid Band Is Not a State - Electronic Circuits IV: Digital Logic Signals and Switch Networks Step by Step

A middle voltage is rejected in this ideal logic model instead of being guessed into LOW or HIGH. Exact arithmetic here means exact results for the stated model inputs; measured inputs still carry uncertainty and significant-figure limits.

highlighted = computed this step

A middle voltage is rejected

An input of 2 volts is above the low threshold and below the high threshold.

1\ \text{V} < 2\ \text{V} < 4\ \text{V}

INVALID is not a third logic state

The model rejects this input before it can drive a gate. That keeps later truth tables from silently coercing the value.

\text{INVALID input} \Rightarrow \text{no gate row}